The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1999
Filed:
Dec. 16, 1997
Gary S Gibson, Tucson, AZ (US);
Burr-Brown Corporation, Tucson, AZ (US);
Abstract
A push-pull output stage includes an NPN pull-up transistor (Q6) and an NPN pull-down transistor (Q7) connected to an output. A compensation capacitor 17 is coupled between the collector and base of the pull-down transistor. A differential input stage includes emitter-coupled first (Q2) and second (Q3) NPN input transistors each coupled by a degeneration resistor to a constant current source. A base of the first NPN input transistor (Q2) is coupled to receive a shifted input voltage (V.sub.IN), and a base of the second NPN input transistor is coupled to the output conductor (3). The collectors of the first (Q2) and second (Q3) input transistors are connected to the sources of a folded cascode circuit including first (J1) and second (J2) cascode P-channel JFETs, respectively, the drains of which are connected to a current mirror output transistor (Q5) and a current mirror control transistor (Q4), respectively. The collector of the current mirror output transistor (Q5) is connected to the base of the pull-down transistor (Q7). The voltage gain of the output stage is determined primarily by the degeneration resistors and the compensation capacitor and hence is quite independent of the load impedance, and therefore provides stable circuit operation. A shoot-through current limiting circuit includes a capacitor and a resistor coupled between the input (V.sub.IN) and the base and collector of the current mirror control transistor (Q4).