The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1999
Filed:
Feb. 27, 1997
James M Preston, Raleigh, NC (US);
Alcatel Alsthom Compagnie Generale d'Electricite, Paris, FR;
Abstract
ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique is a useful interface but does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. The invention provides an extension of the boundary-scan technique currently implemented to provide improved ASIC testability. The Collateral ASIC Test (method and logic) implemented in a boundary-scan device according to the invention makes possible a test process standardization to ASIC design and testing.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile