The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 1999
Filed:
May. 01, 1997
Nathalie Pereira, Eaubonne, FR;
Bertrand DeBray, Maisons Laffitte, FR;
Alcatel Telspace, Nanterre Cedex, FR;
Abstract
The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal F.sub.ref in which some transitions are missing. The loop includes a first divide-by-M frequency divider receiving the clock F.sub.ref and delivering a signal of frequency F.sub.ref /M; a phase comparator providing a phase error signal from the signal of frequency F.sub.ref /M, and the output signal from a second divide-by-M frequency divider; a divide-by-K frequency divider providing a signal of frequency F.sub.k from a local oscillator signal of frequency F.sub.oL receiving the phase error signal as a control signal; an adder-counter of the division ratio p/q receiving the local oscillator signal of frequency F.sub.oL and delivering a signal of frequency F.sub.o equal to F.sub.oL *p/q; a mixer delivering a signal of frequency F.sub.n equal to F.sub.o -F.sub.k on the basis of signal of frequency F.sub.k and the signal of frequency F.sub.o ; and a divide-by-N frequency divider synchronized by F.sub.oL, receiving the signal of frequency F.sub.n, and delivering a recovered clock to the second divide-by-M frequency divider.