The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 1999

Filed:

Jul. 25, 1997
Applicant:
Inventors:

Franklyn H Story, Chandler, AZ (US);

Koichi Eugene Nomura, Phoenix, AZ (US);

Michael James Fickes, Tempe, AZ (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G06F / ;
U.S. Cl.
CPC ...
371 221 ; 39518319 ; 371 225 ;
Abstract

A testing apparatus and method are for testing a plurality of logic blocks within an integrated circuit. The integrated circuit includes a test data input bus, a test data output bus coupled to the output of each logic block, and test enable means which includes selection means coupled between the plurality of logic blocks and the test data input bus. The test enable means selects a first logic block from the plurality of logic blocks, and the selection means selectively inputs to each logic block either normal operating input or the test data. The test results are received from the first logic block through the test data output bus.


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