Non-volatile semiconductor memory device

Abstract

It is an object of the invention to provided an electrically erasable and programmable non-volatile semiconductor memory device, in which misread of a datum stored in a memory cell can be avoided by suppressing floating of the potentials of a memory cell source wire and a word wire in case that the operation of the memory device shifts from erasing pulse application to erase verify. Two transistors with different current-driving capabilities are connected in parallel and inserted between the memory cell source wire and the ground plane. When the operation of the memory device shifts from erasing pulse application to erase verify, a N-type transistor with lower current-driving capability turns on at fist, thereby the potential of the memory cell source wire is slowly reduced, and the other transistor with higher current-driving capability turns on afterward. After the memory cell source wire is connected with the ground plane and its potential is perfectly stabilized, the datum stored in the memory cell can be normally read.