The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 1999

Filed:

Nov. 05, 1997
Applicant:
Inventors:

Naoki Taniguchi, Kanagawa-ken, JP;

Kenjiro Kanayama, Kanagawa-ken, JP;

Tsukasa Miyawaki, Kanagawa-ken, JP;

Hidekazu Saito, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03L / ;
U.S. Cl.
CPC ...
331 14 ; 331 18 ; 331 49 ; 331 74 ; 331158 ; 331D / ; 331D / ;
Abstract

An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.


Find Patent Forward Citations

Taniguchi, Naoki. (1999). Clock generator in which external oscillator is disabled after internal (U.S. Patent No. 5936473). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5936473

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…