The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 1999

Filed:

Dec. 22, 1995
Applicant:
Inventors:

Raffaele Costa, Milan, IT;

Anna Faldarini, Sondrio, IT;

Laura Formenti, Cabiate, IT;

Assignee:

STMicroelectronics, S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
708625 ; 708626 ;
Abstract

A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.


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