The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 1999

Filed:

Jul. 03, 1996
Applicant:
Inventors:

Toshio Tanaka, Ebina, JP;

Kazuhisa Ishida, Owariasahi, JP;

Tetsuro Kiyomatsu, Seto, JP;

Shigeo Tsujioka, Fujisawa, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395308 ; 395287 ; 395306 ;
Abstract

In a computer system having a double PCI bus configuration, an inter-bus control circuit for relaying a first PCI bus and a second PCI bus is provided with a memory control mechanism common to devices connected to the second PCI bus and an interrupt control mechanism for controlling interrupts between local processors, in addition to a control function for controlling the buses. The inter-bus control circuit having the above mechanisms can be implemented by a single-chip integrated circuit. The integrated inter-bus control circuit prevents the use of a plurality of identical decoder circuits, an increase in the number of parts, and an increase in mounting area, thus providing a compact and low price computer system.


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