Memory with reduced wire connections

Abstract

In memory systems embodying the invention a controller/sequencer circuit converts a multiplicity of control signals into a serial stream of control signals which are carried from the controller/sequencer circuit via a single ('data') line to the data input of a control path (e.g., a multi-stage shift register) which is disposed in proximity to a functions generator (e.g., a voltages generator). After the control path is serially loaded with a selected number of control signals, the control signals are selectively applied, in parallel, to the functions generator. Where the control path is a shift register, three control lines are routed from the controller/sequencer to the shift register. One line carries the serial control signals to the input of the shift register; one line (i.e., a shift line) carries shift signals for causing the transfer of the control signals along the shift register stages; and one line (i.e., a select line) is used to selectively transfer control signals accumulated in the shift register to the voltages generator.