The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 1999

Filed:

Nov. 03, 1997
Applicant:
Inventor:

Nianxiong Tan, Sollentuna, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341144 ; 341148 ;
Abstract

High-speed and high accuracy digital-to-analog (D/A) converters find many applications in signal processing. For wideband telecommunication systems, there is a strong demand on high-performance D/A converters. With the design of the present invention it is enabled to prevent distortions and intermodulations for high-speed and high-accuracy digital-to-analog (D/A) converters for telecommunication applications, where the requirements on distortion and intermodulation can be very stringent. By combining segmentation for MSBs and binary weighting for LSBs a high-performance digital-to-analog conversion architecture can be achieved, where a delay for the binary weighted LSBs is used to equalize a delay introduced by segmentation and where all bit switches (14) are clocked with a tree-like-clock distribution network (11). New floor plans for CMOS, BiCMOS and bipolar implementation are thus invented and circuits for CMOS bit switches and current sources are also disclosed.


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