Method and apparatus for dynamically calculating degrees of fullness of

Abstract

An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- x.sub.-- words.sub.-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided. A write Bus Request Enable Generator provides a write bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- y.sub.-- words.sub.-- empty Flag Generator provides a plurality of flags, which indicate degrees of emptiness of the second buffer to the second circuitry.