The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 1999
Filed:
Feb. 27, 1997
Robert A Kertis, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A signal multiplier is provided for use in multiplying an analog differential signal. The analog differential signal is defined by a first analog attribute and a second analog attribute. Preferably, a means is provided for generating a first current which corresponds to the first analog attribute. Additionally, a means is provided for generating a second current which corresponds to the second analog attribute. A first amplifier member is provided for receiving the first current as an input and providing as an output a multiple of the first current. Additionally, a second amplifier is provided for receiving the second current as an input and producing as an output a multiple of the second current. A tuneable multiplier member is provided for determining the multiple over a predetermined range of multiples. A means for maintaining a substantially linear response of the signal multiplier is also provided. The means for maintaining the substantially linear response of the multiplier provides at least approximately two orders of magnitude in multiplication. The means for maintaining a substantially linear response of the signal multiplier includes a means for utilizing base current cancellation in order to minimize the influence of particular base currents from particular analog circuit components which would otherwise limit the linear response of the analog signal multiplier of the present invention.