The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1999
Filed:
Oct. 31, 1997
Applicant:
Inventors:
Katsuhiko Sato, Yokohama, JP;
Shinji Miyano, Yokohama, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 365 51 ; 365 52 ; 365 63 ; 257203 ; 257909 ;
Abstract
An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.