The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1999
Filed:
Aug. 26, 1998
E Ajith Amerasekera, Plano, TX (US);
Raoul B Salem, Redwood City, CA (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.