The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1999
Filed:
Jun. 10, 1997
Wagdi W Abadeer, Jericho, VT (US);
George Maria Braceras, Colchester, VT (US);
John Connor, Burlington, VT (US);
Donald Albert Evans, Allentown, PA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A CMOS off-chip driver circuit and a method of operating the circuit are provided. The circuit has two pull-down transistors and two pull-up transistors, each pull-up transistor has a gate. A voltage source provides voltage at a logic-high output voltage of approximately 3.3 volts. An output terminal is provided. Initially, a logic-low output voltage is applied to the gate of each of the two pull-up transistors. A condition is detected in which the voltage of the output terminal is greater than a predetermined threshold voltage. The predetermined threshold voltage is between approximately 2.5 volts and approximately 3.3 volts. The voltage applied to the gate of each of the pull-up transistors is raised to an intermediate level that is greater than the logic-low output voltage and less than the logic-high output voltage while the condition is detected. The intermediate level may be approximately 1.5 volts. A clamping mechanism is provided for sinking current from the output terminal to the voltage source, when the voltage of the output terminal is greater than the logic-high output voltage. The clamping mechanism sources current to the output terminal from a ground conductor that provides the logic-low output voltage to the pull-down transistor, when the voltage of the output terminal is less than the logic-low output voltage.