The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 1999

Filed:

Jun. 11, 1998
Applicant:
Inventors:

Abhijeet V Chavan, Ann Arbor, MI (US);

Kensall D Wise, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257417 ; 257254 ;
Abstract

A semiconductor device that uses polysilicon as an electrostatic bonding medium and as a lead transfer for multiple lead connection to one or more electrical devices within a vacuum sealed chamber. A semiconductor region, such as a heavily built P++ silicon region, is bonded to a glass substrate of the device. The semiconductor region includes a recess that defines a chamber between the semiconductor region and the substrate. Multiple internal electrodes or lead transfers within the chamber pass through separate electrical connection regions in a polysilicon sealing layer that seals the semiconductor region to the substrate. In one embodiment, each of the separate electrical connection regions includes an upper polysilicon region and a lower polysilicon region separated by a dielectric layer. The lower polysilicon region includes a first separate polysilicon region electrically connected to one of the internal leads and a second separate polysilicon region electrically connected to an external lead. Holes are formed in the dielectric layer so that the first and second separate polysilicon regions are electrically connected to the upper polysilicon region. A sealing polysilicon region positioned between the first and second separate polysilicon regions provides the seal, and is electrically isolated from the first and second polysilicon regions. Therefore, the combination of the first polysilicon region, the upper polysilicon region and the second polysilicon region forms a bridge over the sealing polysilicon region to electrically connect the internal lead to the external lead. Isolation trenches are provided in the upper polysilicon region to electrically separate the electrical connection regions.


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Chavan, Abhijeet. (1999). Batch processed multi-lead vacuum packaging for integrated sensors and (U.S. Patent No. 5929497). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5929497

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