The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1999
Filed:
Mar. 21, 1997
Applicant:
Inventor:
Hiroaki Tsutsui, Tokyo, JP;
Assignee:
NEC Corporation, , JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257276 ; 257275 ; 257712 ; 257713 ;
Abstract
A GaAs substrate is divided at boundary regions of unit cells of FET chips. With such construction, magnitude of curling of the GaAs substrate due to a difference of thermal expansion coefficients between the GaAs substrate and the PHS upon heating during assembling, can be reduced. In a semiconductor device with a PHS, the magnitude of curling of the semiconductor substrate after assembling can be reduced by reducing stress upon assembling, without causing degradation of reliability.
Tsutsui, Hiroaki. (1999). Field effect transistor with plated heat sink on a fet chip (U.S. Patent No. 5925901). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5925901
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