The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 1999

Filed:

Mar. 20, 1997
Applicant:
Inventors:

Susumu Yamada, Moriguchi, JP;

Toru Watanabe, Moriguchi, JP;

Shinichi Yamasaki, Moriguchi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
714 14 ; 714 42 ; 714 54 ; 711152 ; 711155 ;
Abstract

When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.


Find Patent Forward Citations

Yamada, Susumu. (1999). Microcomputer capable of preventing writing errors in a non-volatile (U.S. Patent No. 5925139). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5925139

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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