The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 1999

Filed:

Feb. 28, 1997
Applicant:
Inventor:

Ryoji Maruyama, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ;
U.S. Cl.
CPC ...
702 60 ; 324141 ;
Abstract

First and second 1-bit A/D converters convert respective input voltages being in direct proportion to voltage and current of a measurement system into respective 1 bit codes. First and second up-down counters whose up/down count in respective clock terminals are controlled in accordance with respective 1 bit codes which are output from the first and second 1-bit A/D converters, and output A/D converted values of the respective input voltages. A latch holds data one clock prior to currently input data and outputs the data. An adder-subtractor adds and subtracts respective output data of the first and second up-down counters and a numerical value 1 to and from output data of the latch under control of respective output data of the first and second 1-bit A/D converters and an exclusive OR value of the respective output data and outputs arithmetic data which being in proportion to a product of the respective input voltages to the latch. An adder integrates the output data of the latch.


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