Multifunctional execution unit having independently operable adder and

Abstract

Floating point performance in a VLIW processor is increased through concatenation of two floating point units, one an adder and another a multiplier, which execute independently of one another but which operate in cooperation for certain combinations of issued operations. In particular, the floating point adder and the floating point multiplier may be activated individually by very long instruction words, which are also called wide instructions, that issue operations to either unit or both units at one time. For other wide instructions, both the floating point adder and the floating point multiplier may be sequentially activated by a single instruction with three operands. The first two operands are used by one of the units, either the floating point adder or the floating point multiplier, and the unit is activated. The result generated by the activated unit and the third operand are applied as operands for usage by one of the units, again either the floating point adder or the floating point multiplier, and the unit is activated. In this manner, a single instruction activates the floating point multiplier and the floating point adder in combination for execution of two operations. Each of the floating point adder and the floating point multiplier execute once or either executes twice by the issue of a single instruction.