The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1999
Filed:
May. 01, 1997
Hemanth G Kanekal, San Jose, CA (US);
Cirrus Logic, Inc., Fremont, CA (US);
Abstract
The present invention is implemented in a peripheral component coupled to a peripheral component interconnect (PCI) bus. The peripheral component includes an internal device operating in an internal clock domain while the PCI bus operates in a PCI clock domain. The system of the present invention efficiently interfaces the internal device with the PCI bus. The present invention generates and couples a request for PCI bus ownership, originating from the internal device, to the PCI bus. The present invention then determines whether the PCI bus is idle or busy. Where the PCI bus is idle, a proceed signal is generated for the internal device. Where the PCI bus is busy, a do not proceed signal for the internal device is generated. Both the proceed and the do not proceed signals are synchronous to the internal clock domain. The PCI bus is acquired and a data transaction from the internal device is executed when the internal device receives the proceed signal. The data transaction is translated from the internal clock domain to the PCI clock domain. The data transaction is postponed when the internal device receives the do not proceed signal. The present invention causes a retry for an external data transaction directed at the internal device to prevent the external data transaction from conflicting with the data transaction from the internal device. In so doing, the system of the present invention ensures the internal device is properly and efficiently interfaced to the PCI bus regardless of the differing clock domains.