Clock doubler circuit with duty cycle control

Abstract

A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer. The plurality of control bits thereupon causes the multiplexer to selectively pass one of the outputs of the primary delay element or plurality of secondary elements as its output. The exclusive-OR logically combines a system clock signal and the output of the multiplexer to generate a clock signal at twice the frequency of the system clock signal and duty cycle as determined by the control bits and the delays of the primary delay element and the plurality of secondary delay elements.