The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 1999

Filed:

Apr. 30, 1998
Applicant:
Inventors:

Charles R Erickson, Fremont, CA (US);

Robert O Conn, Los Gatos, CA (US);

Lois D Cartier, Los Gatos, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G06F / ;
U.S. Cl.
CPC ...
365236 ; 36518902 ; 326 38 ;
Abstract

A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ('FPGA'). In one embodiment, the memory device is a Read-Only Memory ('ROM') that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.


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