The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 1999

Filed:

Jun. 03, 1997
Applicant:
Inventor:

Peter H Voss, Aromas, CA (US);

Assignee:

Cypress Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365154 ; 365104 ; 365156 ;
Abstract

A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function. Since, the first block of RAM cells may store RAM data when the device operates in RAM mode, and may store preprogrammed ROM data when reset by the select circuit, the first block of RAM cells may have a storage capacity that is greater than the number of RAM cells in the first block.


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