The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1999
Filed:
Jan. 02, 1997
Morgan Paul Smith, San Francisco, CA (US);
Paul Raj Findley, Cupertino, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The present invention provides a computer implemented method and apparatus for determining the total capacitance of a primary interconnect line positioned between top and bottom ground planes. The primary interconnect line is positioned at a distance, H1, from the bottom ground plane and at a distance, H2, from the top ground plane. Preferred embodiments of the present invention include computer implemented processes for empirically determining the total capacitance of the primary interconnect line both with and without neighboring interconnect lines present. Core steps of the present invention include partitioning of a parameter representing fringe capacitance which is due to fringe electric fields induced between sidewalls of the primary interconnect line and the top and bottom ground planes. In the present invention, the fringing capacitance is partitioned into a top fringe capacitance, C.sub.f (H2), which is due to electric fields induced between the sidewalls of the interconnect line and the top ground plane, and a bottom fringe capacitance, C.sub.f (H1), which due to electric fields induced between the sidewalls of the interconnect line and the bottom ground plane. The total fringing capacitance is modeled according to: