The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 1999

Filed:

Oct. 02, 1997
Applicant:
Inventor:

David L Larkin, Lubbock, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438692 ; 438257 ; 438262 ; 438710 ;
Abstract

A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.


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