The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 1999
Filed:
Jul. 22, 1996
Timothy D Dorney, Houston, TX (US);
Texas Istruments Incorporated, Dallas, TX (US);
Abstract
A reduced silicon area, wide input/output (I/O) comparitor method and apparatus for design-for-test applications includes a plurality of input/output pins (60) and plural arrays of addressable storage cells (32-46). A page mode writing circuit provides, through a common data-in lead (30), plural copies of a test data bit, applied through one of the pins (30), for storage in addressed storage cells (32-46) along a row in each of the arrays of storage cells. A circuit receives an expected data bit (ED), and a readout circuit reads out the stored test data bit from the addressed storage cells along the row in each of the arrays of storage cells. A PRW signal generator (154) responds to a column address change to establish a first potential state on all four quadrant-specific common lines (102, 408, 411, and 413). A plurality of multiplexer circuits (230), each multiplexer circuit associated with two different arrays of storage cells, are arranged to combine the multiple data bits from the associated arrays (32-46) to a reduced number of outputs to the plural comparitors circuits (242, 244, 248, and 250).