Alarm signal processing circuit

Abstract

An alarm signal processing circuit is provided for an integrated circuit having alarm signal generating circuitry for generating alarm signals having active and inactive states, and for connecting to a microprocessor. An alarm signal is stored in an alarm register which stores an inactive alarm signal until receipt of an active alarm signal, whereupon it stores the active alarm signal until receipt of an alarm register reset signal from the microprocessor. The alarm signal is also detected by an alarm detector which generates an event signal which is active when the alarm signal changes its status. An event register stores an inactive event signal until receipt of an active event signal, whereupon it stores the active event signal until receipt of an event register reset signal from the microprocessor. The event register outputs an event interrupt signal which is active when the stored event signal is active. The event interrupt signal is output by an event interrupt output means for use by the microprocessor. The event interrupt output means is controlled by an event enable register which stores an event enabling signal or an event disabling signal in response to an event enable control signal received from the microprocessor. The event interrupt output means is enabled to output an active event interrupt signal when the event enable register stores the event enabling signal, and disabled from outputting the active event interrupt signal when the event enable register stores the event disabling signal. The alarm register and the event register are accessible by the microprocessor to read the stored alarm signal or the stored event signal.