The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 1999
Filed:
Dec. 24, 1996
James Arthur Bailey, Allentown, PA (US);
Angelo Rocco Mastrocola, West Lawn, PA (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
An improved complementary logic driven level shifter which typically improves switching speed over the prior art diode-type circuit, and allows for symmetrical delays for both high-to-low and low-to-high transitions, thus reducing settling times. The complementary CMOS and not-CMOS inputs to the level shifter are applied to the gates of a pair of P-channel FETs and also to the gates of a pair of N-channel FETs. The sources of the P-channel FETs are coupled to a current source. The drain of each P-channel FET is coupled to the drain of the N-channel FET to which its gate is coupled, and also to the anode of a diode. The cathodes of the two diodes, and the sources of the N-channel FETs are coupled together to the anode of a grounded cathode diode. The output SELECT is the common connection point of the drains of the FETs whose gates are coupled to not-CMOS, and the complementary not-SELECT output is the drains of the FETs whose gates are coupled to CMOS. In a second embodiment, the two diodes across the N-channel FETs are replaced by a diode from the current source to the anode of the grounded-cathode diode.