Thin-film transistor display devices having coplanar gate and drain lines

Abstract

Methods of forming thin-film transistor display devices having coplanar gate and drain lines include the steps of forming gate and data lines using the same level of metallization and also using an etch stop layer to protect the active regions of the TFTs in each of the display cells. A preferred method includes the steps of forming a first conductive layer on a substrate and then patterning the first conductive layer to define a plurality of parallel gate lines and a plurality of parallel data lines which each comprise a plurality of data line segments. A first electrically insulating layer is then formed on the data and gate lines. A first undoped amorphous silicon (a-Si) layer is then formed on the first electrically insulating layer and patterned to define an amorphous silicon active region for each cell. A second electrically insulating layer is then formed on the amorphous silicon active region. The first and second electrically insulating layers are then patterned to expose source and drain portions of the amorphous silicon active region and define at least one data line contact hole which exposes a portion of a data line segment for each cell. A second amorphous silicon layer of first conductivity type (e.g., N-type) is then formed on the exposed source and drain portions of the amorphous silicon active region and in the data line contact holes. An optically transparent conductive layer (e.g., indium-tin-oxide (ITO)) is then formed on the second amorphous silicon layer. Then, the optically transparent conductive layer and the doped second amorphous silicon layer are etched to define a source electrode (which electrically connects the data line to the source portion of the amorphous silicon active region) and define a pixel electrode (which is electrically connected to the drain portion of the amorphous silicon active region).