System for determining the average latency of pending pipelined or split

Abstract

Logic for determining the average latency of pending pipelined and split bus transactions within a computer system including a bus, such as an Intel Pentium Pro or P6 bus, which supports pipelined and split bus transactions. The logic includes a first counter connected to the bus, and containing a TOTAL QUALIFIED CYCLES count value which is incremented on the start of every qualified bus cycle placed on the bus; logic for determining a cycle COUNT-BY-VALUE representing the number of outstanding or pending qualified bus cycles during any bus cycle; and a second counter which is incremented at the start of every qualified bus cycle occurring during the sample period by the number of outstanding qualified bus cycles to provide a TOTAL LATENCY CLOCKS count value. Divider logic is connected to receive the TOTAL QUALIFIED CYCLES count value from the first counter and the TOTAL LATENCY CLOCKS value from the second counter and divide the TOTAL QUALIFIED CYCLES count value into the TOTAL LATENCY CLOCK value to determine the average number of clocks of latency, or average number of pending bus cycles, per qualified bus cycle.