The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 1999
Filed:
Mar. 12, 1997
Nat Seshan, Houston, TX (US);
Douglas E Deao, Brookshire, TX (US);
Gary L Swoboda, Sugarland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The invention provides a method for interrupting processing by a processor. The method includes the step of requesting an analysis interrupt by setting a bit in a register in the processor (119), the bit associated with an analysis interrupt, the analysis interrupt having a configurable priority. The method also includes the step of detecting the analysis interrupt request. The method further comprises assigning an assigned priority level (114) to the analysis interrupt from a range of priority levels and processing the analysis interrupt (124) based on the assigned priority level. The invention also provides a processor having a memory unit (14, 16) and a central processing unit (12) operable to access the memory unit. The central processing unit (12) includes an interrupt priority parameter storage system (80) for storing an interrupt priority parameter. The central processing unit further includes a configurable interrupt detection system (36) operable in combination with the central processing unit to detect a configurable interrupt. The central processing unit also includes an interrupt handling system (38) operable in combination with the central processing unit to process a detected configurable interrupt with a first priority level if the interrupt priority parameter has a first value and further operable to process the detected configurable interrupt with a second priority level if the interrupt priority parameter has a second value, the first priority level different from the second priority level and the first value different from the second value. The central processing unit also includes at least three separate interrupt return pointer registers (74, 76, 78) for storing addresses associated with resuming processing of the processor interrupted by an interrupt.