Apparatus for reducing a computational result to the range boundaries of

Abstract

The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state. The program sets a first mask signal to have 16 lower bits in an ON position when the intermediate signal is within the range boundary of a 16-bit signed integer. If the intermediate signal exceeds the maximum range boundary of 32767, the first mask signal is set to have its 31st through 17th bits in the ON position. If the intermediate signal exceeds the minimum range boundary of -32767, the first mask signal is set to have its 32nd bit position set to the ON position The second mask signal has a value that is equal to the first mask value bit-shifted 16 bit positions to the right. Finally, the program bitwise ANDs the original intermediate signal with the first mask signal to obtain a translated data signal, and bitwise ORs the translated data signal with the second mask signal.