The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 1999
Filed:
May. 09, 1996
Ming Chun Chen, Milpitas, CA (US);
Yung-Tao Lin, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Defect scanner sensitivity and accuracy are improved for light scattering defect scanners and pattern matching defect scanners by calibrating the defect scanners to each die on a wafer using preset marks on the corresponding die. The marks have a predetermined size based on the sensitivity of the defect scanners and a predetermined position relative to the circuit pattern on the corresponding die. Alignment of the defect scanners to a specific die provides improvement in coordinate accuracy over alignment with respect to an entire wafer. A layout mapping defect filtering system collects defect scan data and determines the interaction between the detected defects and a circuit layout. The layout mapping defect filtering system provides automatic identification in real time of killer defects that cause failure of the completed integrated circuit, and classifies and analyzes defects to identify potential killer defects within specified defect classes to identify defective die. The system provides accurate yield estimation to determine whether a produced wafer should be scrapped, and also provides accumulated data for yield improvement studies including quality control and circuit redesign.