The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1999
Filed:
Nov. 12, 1996
Akira Mineji, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A method of forming shallow diffusion layers in a semiconductor substrate is provided wherein the shallow diffusion layers are positioned in the vicinity of edge portions of a gate electrode and laterally extend from source/drain diffusion layers having a bottom level deeper than the shallow diffusion layers. The above method comprises the following steps. Crystal defects are selectively formed at least in predetermined shallow regions positioned in a surface region of the semiconductor substrate and in the vicinity of the edge portions of the gate electrode. The predetermined shallow regions are laterally in contact with impurity-introduced deep regions having been formed. The predetermined shallow regions have a bottom level shallower than the impurity-introduced deep regions. Subsequently, the semiconductor substrate is subjected to a heat treatment not only to cause a vertical diffusion of an impurity from the impurity-introduced regions so as to selectively form the source/drain diffusion layers but also to cause a rate-increased lateral diffusion of the impurity from the impurity-introduced regions through the predetermined shallow regions so as to selectively form the shallow diffusion layers.