Serial speed-matching buffer utilizing plurality of registers where each

Abstract

A serial speed-matching buffer for transferring data signals between a selectable one of multiple transferring units to one or more receiving units. The serial speed-matching buffer has a plurality of registers which may each be selectably configured in load mode to receive data signals from selectable ones of the transferring units. Data signals provided to the speed-matching buffer from a selectable one of the transferring units may be made available to the receiving unit during the next clock period. This is an improvement over a rank-of-registers speed-matching buffer which generally inflicts a delay prior to the first word of any transfer. When not conditioned in load mode, each of the registers defaults to a serial chain mode in which data signals may be received from an associated adjacent one of the registers, and wherein a predetermined one of the registers provides data signals at the receiving rate. Any register not containing valid buffered data signals is available to receive data signals from a transferring unit, thereby resulting in a design which requires fewer registers. Because the registers default to a serial chain mode when not receiving data from a selectable one of the transferring units, control logic for the buffer is simplified.