The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1999
Filed:
Dec. 05, 1996
Peter Chambers, Scottsdale, AZ (US);
Edward Michael Petryk, Pheonix, AZ (US);
Scott Edward Harrow, Scottsdale, AZ (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The present invention comprises a multiple functional block integrated circuit device for connecting to an external peripheral component interconnect (PCI) bus. The present invention includes an integrated circuit adapted to be coupled to an external PCI bus. The integrated circuit includes a plurality of functional blocks. Each of the plurality of functional blocks performs a function and comprises either a master functional block or a target functional block. A target bus adapted to transmit data signals is integral with the integrated circuit. The target bus is coupled to each of the plurality of functional blocks. A master bus adapted to transmit data signals is also integral with the integrated circuit. The master bus is coupled to each master functional block. A target bus interface integral with the integrated circuit is coupled to the target bus. The target bus interface is adapted to be coupled to the external PCI bus and to each of the plurality of functional blocks and interfaces each of the plurality of functional blocks to the external PCI bus. A master bus interface integral with the integrated circuit is coupled to the master bus. The master bus interface is adapted to be coupled to the external PCI bus and to each master functional block and interfaces each master functional block to the external PCI Bus.