The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1999
Filed:
Feb. 28, 1997
Christian Ponte, La Colle sur Loup, FR;
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system. A control logic circuit is also included in the smart debug interface circuit of the present invention. The control logic circuit is coupled to the instruction register, the data register, and the interface port. The control logic circuit interfaces a debugging program on the host computer system to the programmable digital processor. Additionally, the control logic circuit interfaces the debugging program with the programmable digital processor without imposing boundary scan bus delay on the instruction bus or the data bus.