The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1999
Filed:
Oct. 14, 1997
Applicant:
Inventors:
James Lutley, Southampton, GB;
Sandeep Pant, Hampshire, GB;
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
361111 ; 326 81 ; 327328 ;
Abstract
The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.