Charge balanced ramp with improved signal linearity

Abstract

A ramp circuit repeatedly generates a substantially linear ramp signal. Ramp switch junction capacitance that otherwise causes a nonlinear output is compensated to improve signal linearity and enable faster retriggering. The ramp includes an output transistor, with its output coupled to a current source and a charge storage device. The output charge storage device charges when the transistor is on. When the transistor is turned off, the output charge storage device discharges, resulting in the changing ramp signal. The output transistor inherently includes a junction capacitance, which causes a nonlinearity in the discharge of the charge storage device. This nonlinearity appears as a quick drop in the ramp signal relative to the slower rate of steady-state decrease. This nonlinearity is prevented, however, by compensating for the output transistor's junction capacitance. In one embodiment, compensation circuitry includes a compensation capacitor coupled between the ramp output and a pull-up register attached to a power supply voltage. An input stage includes two transistors, each having a power supply node, an input node, and an output node. The transistors are interconnected at their output nodes, coupled to electrical ground via a current source power supply. The power supply node of the first transistor is coupled to the node connecting the pull-up resistor and the compensation capacitor. The power supply node of the second transistor is coupled to a second pull-up register attached to the power supply. The first transistor receives a reset signal input to the ramp, whereas the second transistor receives a trigger signal that is the inverse of the reset signal.