The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 1999

Filed:

Jul. 07, 1995
Applicant:
Inventors:

Harutsugu Fukumoto, Anjo, JP;

Hiroaki Tanaka, Okazaki, JP;

Kazuhiro Tsuruta, Toyoake, JP;

Assignee:

Nippondenso Co., Ltd, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257351 ; 257374 ; 257508 ;
Abstract

A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs. A bias voltage switching circuit applies electric potentials to the bias electrodes for the P-channel and the N-channel to increase the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in a waiting state and applies the electric potentials to the bias electrodes for the P-channel and the N-channel to reduce the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in an operating state.


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