The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1999
Filed:
Jun. 30, 1997
Hwa-sook Shin, Kyungki-do, KR;
Kyeong-koo Chi, Kyungki-do, KR;
Samsung Eletronics Co., Ltd., Suwon, KR;
Abstract
Methods of forming electrically conductive lines include the steps of forming a first electrically insulating layer (e.g., SiO.sub.2) on a face of a semiconductor substrate and then forming a layer of polycrystalline silicon (polysilicon) as a blanket layer on the first electrically insulating layer. A metal silicide layer (e.g., TiSix) is then formed on the polysilicon layer by reacting the polysilicon layer with an appropriate metal such as titanium (Ti) using a thermal treatment step. Thereafter, a second electrically insulating layer (e.g., SiO.sub.2, Si.sub.3 N.sub.4) is formed on the metal silicide layer using conventional techniques. A layer of photoresist is then deposited onto the second electrically insulating layer and patterned as an etching mask using conventional photolithographic processing steps. The second electrically insulating layer, metal silicide layer and polysilicon layers are then sequentially etched to define a plurality of spaced conductive lines which each comprise a composite of a polysilicon layer and metal silicide layer thereon. Preferably, the metal silicide layer and the polysilicon layer are sequentially dry etched by exposing these layers to a composite gas containing Cl.sub.2 and N.sub.2 gases which are provided at preferred volumetric flow rates and temperatures greater than 23.degree. C. (i.e., room temperature) so that the amount of polymer residue generated during the etching step is sufficient to protect the interface between the metal silicide layer and the polysilicon layer from lateral overetching but not so excessive as to prevent complete removal of those portions of the metal silicide and polysilicon layers exposed by the openings in the patterned layer of photoresist.