Multiple bus master computer system employing a shared address

Abstract

A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe. If a page fault occurs, the central processor communicates to the alternative bus master to release the translation request until the central processor performs a table walk. After page fault recovery, the central processor communicates to the alternative bus master to reassert the translation request so that the translation may be completed. Alternative embodiments employ new encoding of preexisting signals to signal requests/acknowledgments for translation.