Rom/ram overlap circuit

Abstract

A control circuit initiates operation of the ROM array and the RAM array in an ATD circuit includes an EXCLUSIVE NOR circuit having: a RAM SELECT input terminal for receiving a RAM SELECT (RAMCS*) signal, a ROM SELECT input terminal for receiving a ROM SELECT (ROMCS*) signal, and having a chip enable output terminal at which is provided a chip enable signal (CE) at an active LOW state whenever the RAMCS* and the ROMCS* are both the same logic level, both either HIGH or LOW. The control circuit further includes a compensating pulse circuit to compensate for operation of the EXCLUSIVE NOR circuit during a dead-time interval in which the EXCLUSIVE NOR circuit does not function when the RAMCS* and the RAMCS* both change during that dead-time interval. The compensating circuit includes a two pulse generators, each generating an output pulse having a pulse width which is greater than the dead-time interval of the EXCLUSIVE NOR circuit. Each pulse generator provides an output pulse when the RAM/ROM SELECT signal goes to a one level after the ROM/RAM SELECT signal has been at a one level and the pulse generator also provides an output pulse when the ROM/RAM SELECT signal switches to a zero level such that the zero transition is delayed by an inverter chain, which quickly passes through a zero-to-one transition and which slowly passes through a one-to-zero transition such that the pulse generator provides an output pulse with a width determined by the slow passage from the one-to-zero transition.