The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1999
Filed:
Jun. 26, 1996
Applicant:
Inventors:
Hyun Sik Jang, Kyoungkido, KR;
Dong Seuk Park, Kyoungkido, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36478702 ; 36478703 ;
Abstract
A carry increment adder (CIA) using a clock phase in which the CIA performs at an increased speed but uses a much smaller chip area than a general fast adder structure. In the CIA from 1 to N partial adder modules (RCA) which generate partial sum and partial carry value using desired bits of two input data (a, b) as a module. The wider the addition bits width, the greater the speed and the smaller the chip area used.
Jang, Hyun. (1999). Carry increment adder using clock phase (U.S. Patent No. 5912833). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5912833
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