Graphical image convolution using multiple pipelines

Abstract

A parallel processor which is capable of partitioned multiplication and partitioned addition operations convolves multiple pixels in parallel. The parallel processor includes a load and store pipeline of a load and store unit which retrieves data from and stores data to memory and one or more arithmetic processing pipelines of an arithmetic processing unit which aligns data and performs partitioned multiplication and partitioned addition operations. A patch of pixels from a source image are convolved substantially simultaneously in the arithmetic processing pipeline of the processor by execution of the partitioned multiplication and partitioned addition operations. At substantially the same time, a subsequent patch of pixels from the source image are read by the load and store unit of the processor. The subsequent patch of the source image is a patch which is aligned with respect to a secondary index and is incremented along a primary index to avoid excessive cache misses when retrieving pixel data for convolution. Reading of pixel data is performed in the load and store pipeline of the processor while the arithmetic processing pipeline substantially simultaneously performs partitioned arithmetic operations on the pixel data to thereby convolve the pixel data.