The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1999
Filed:
Mar. 21, 1997
Tamas I Pattantyus, Dallas, TX (US);
AlliedSignal Inc., Morristown, NJ (US);
Abstract
A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is above the first predetermined level. The output register is active when the level of the clock pulse signal is above a second predetermined level and inactive when the clock pulse signal is below the second predetermined level. There exists a well-defined voltage range during which both the input and output registers are inactive. The transfer of information from the input register to the output register only occurs during the transition from a logic 0 level to a logic 1 level clock pulse signal. The SET and RESET inputs are only enabled when the clock pulse signal is at a logic 0 level. This register management helps to ensure that noise on the clock pulse line does not erroneously trigger the input or output registers and further helps to prevent a race condition from developing between the input and output registers.