The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1999
Filed:
Dec. 09, 1996
Raghunand Bhagwan, Sunnyvale, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop provides a feedback signal to maintain clock frequency, while a second loop provides a feedback signal and controls duty cycle. Two clock signals from a ring oscillator are fed to a level shifter, where each clock signal triggers a respective rising or trailing edge of the output clock signal. The level shifter is provided with a delay for controlling timing of the trailing edge of the output clock signal. The output clock signal is fed to a equi-current buffer where a charge pump, driven by the output clock signal, charges and discharges a capacitor in proportion to the duty cycle of the output clock signal, producing a feedback control voltage. The feedback control voltage is applied to the delay of the level shifter to maintain a substantially 50% duty cycle. The clock circuit of the present invention has improved power supply noise immunity and control voltage headroom for operation at different design frequencies.