Stacked-gate flash eeprom memory devices having mid-channel injection

Abstract

Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first 'source-side' region of second conductivity type (e.g., P+) and a second 'drain-side' region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate. During programming, this EEPROM unit cell provides efficient mid-channel injection at high rates and at relatively low voltage levels and avoids many of the limitations associated with conventional stacked-gate EEPROM devices which typically provide less efficient drain-side injection and require relatively high voltage levels during programming. In particular, mid-channel injection of hot electrons from the channel region to the floating gate (within the stacked-gate electrode) is promoted by tailoring the conductivity of the channel region so that pinch-off occurs at a midpoint in the channel region during programming operations.