The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1999

Filed:

Aug. 05, 1997
Applicant:
Inventors:

Alan H Huggins, Gilroy, CA (US);

William L Devanney, Menlo Park, CA (US);

Chuen-Der Lien, Los Altos Hills, CA (US);

Assignee:

Integrated Device Technology, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 365226 ;
Abstract

A circuit and a method for providing a power supply voltage to a memory circuit during a memory data retention test are provided. In such a circuit, a first power supply terminal and a second power supply terminal are provided together with a plurality of circuit elements, which are coupled to form a current path between the first and second power supply terminals, such that each circuit element contributes a predetermined voltage drop between the first and second power supply terminals when a current flows in said current path. In addition, a shunt device having a control terminal and coupled across one or more of said circuit elements is provided. The control terminal receives a control signal, such that when the control signal is asserted, the shunt device equalizes a voltage across said one or more of said circuit elements. The memory circuit draws its power supply voltage from the second power supply terminal.


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